ZH reported, citing a May 26 report from China Daily.
Huawei Technologies Co has introduced a new semiconductor development framework that it says could allow its premium chips to reach performance levels comparable to 1.4-nanometer process technology by 2031, marking a bold attempt to rethink how chip performance is improved in the post–Moore’s Law era.
The announcement was made at a semiconductor conference in Shanghai, where the company presented its long-term chip architecture roadmap and outlined a new design philosophy it calls the “Tau Scaling Law”.
Moving Beyond Traditional Chip Shrinkage
Traditionally, advances in semiconductor performance have relied on shrinking transistor size — a process known as node scaling. However, Huawei argues that this approach is increasingly constrained by physical and economic limits.
Instead of focusing primarily on reducing transistor dimensions, the new framework emphasizes reducing signal propagation time across devices, circuits, chips and systems. In other words, performance gains are achieved through architectural optimization rather than only manufacturing miniaturization.
He Tingbo, a board member of Huawei and president of its semiconductor division, said the company has already designed and mass-produced 381 chips based on this framework over the past six years, spanning applications from smartphones to artificial intelligence computing.
New Kirin Chip and Multi-Layer Architecture
Huawei also confirmed that it plans to launch a new Kirin smartphone chip this autumn. The chip will reportedly use a multi-layer circuit design aimed at shortening critical signal paths while improving both transistor density and energy efficiency.
The company’s projection suggests that, under this framework, its chips could reach performance density comparable to 1.4nm-class technology by 2031.
Industry observers note that if successful, the approach could represent an alternative pathway for improving chip performance at a time when access to advanced lithography tools remains constrained.
Semiconductor Strategy Amid Global Restrictions
The development comes against the backdrop of ongoing US export controls that have limited China’s access to cutting-edge semiconductor manufacturing equipment, including extreme ultraviolet (EUV) lithography systems.
As a result, Chinese semiconductor companies have been under pressure to explore alternative innovation paths that do not rely solely on traditional fabrication scaling.
While China is widely considered unlikely to match leading-edge manufacturing nodes purely through conventional methods in the near term, experts say architectural innovation could help narrow performance gaps in practical applications.
China’s Push for a Domestic AI Chip Ecosystem
Huawei’s announcement also reflects a broader shift in China’s artificial intelligence and semiconductor ecosystem, where domestic chips are increasingly being integrated into AI development workflows.
For example, in its DeepSeek-V4 technical documentation, Chinese AI firm DeepSeek listed Huawei’s Ascend neural processing unit alongside Nvidia GPUs within the same hardware validation framework. It marked one of the first instances in which a domestic AI chip was positioned at a comparable level in formal technical reporting.
Similarly, other AI developers such as Kimi have explored system architectures designed to reduce token inference costs using domestically developed chip platforms.
These developments suggest a gradual but steady shift toward local computing infrastructure in China’s AI ecosystem, particularly as demand for large-scale model deployment increases.
Industry View: Innovation Under Constraint
Analysts say Huawei’s strategy reflects a broader trend in China’s semiconductor industry: innovation driven by structural constraints.
Roger Sheng, vice-president of research at Gartner, said Chinese chip firms are demonstrating increasing resilience and innovation capability despite external challenges.
Meanwhile, Xing Ziqiang, chief China economist at Morgan Stanley, noted that China’s semiconductor progress is supported by long-term advantages in industrial clustering, engineering talent and large-scale domestic demand. He estimated that China could reach a 50 percent localization rate in GPUs by 2027 or 2028.
A Shift in How Chip Performance Is Defined
Huawei’s “Tau Scaling Law” signals a potential rethinking of how semiconductor performance is measured and improved.
Rather than relying exclusively on shrinking transistor sizes, the framework emphasizes system-level efficiency, circuit design and data flow optimization.
If adopted more widely, such approaches could gradually reshape how chipmakers approach performance gains in an era where traditional scaling is becoming increasingly difficult.
A Long-Term Bet on Alternative Semiconductor Paths
Huawei has positioned its roadmap as a long-term effort to explore alternative semiconductor development pathways, rather than a direct replacement for leading-edge manufacturing processes.
The company also emphasized collaboration, stating that no single organization can solve the challenges of semiconductor development alone.
“We look forward to working closely with scientists, engineers and industry partners around the world,” Huawei said, underscoring the open-ended nature of its research direction.
For now, the announcement reflects both ambition and necessity — an effort to push forward semiconductor innovation in an environment where the rules of scaling are being rewritten.